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? 2007 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? 1 ? ? ? ? ? ? device highlights high performance & high density ? up to 90,000 usable pld gates with up to 316 i/os ? 300 mhz 16-bit counters, 400 mhz datapaths, 160+ mhz fifos ? 0.35 m four-layer metal non-volatile cmos process high speed embedded sram ? up to 22 dual-port ram modules, organized in user-configurable 1,152 bit blocks ? 5 ns access times, each port independently accessible ? fast and efficient for fifo, ram, and rom functions easy to use/fast development cycles ? 100% routable with 100% utilization and complete pin-out stability ? variable-grain logic cells provide high performance and 100% utilization ? comprehensive design tools include high quality verilog/vhdl synthesis advanced i/o capabilities ? interfaces with 3.3 v and 5.0 v devices ? pci compliant with 3.3 v and 5.0 v busses for -1/-2 speed grades ? full jtag boundary scan ? registered i/o cells with individually controlled clocks and output enables up to 316 i/o pins ? 316 bi-directional input/output pins, pci-compliant for 5.0 v and 3.3 v buses for -1/-2 speed grades ? eight high-drive input/distributed network pins eight low-skew distributed networks ? two array clock/control networks are available to the logic cell flip-flop; clock, set, and reset inputs ? each can be driven by an input-only pin ? six global clock/control networks available to the logic cell; f1, clock, set, and reset inputs and the data input, i/o register clock, reset, and enable inputs as well as the output enable control?each can be driven by an input-only, i/o pin, any logic cell output, or i/o cell feedback high performance silicon ? input + logic cell + output total delays under 6 ns ? data path speeds over 400 mhz ? counter speeds over 300 mhz ? fifo speeds over 160+ mhz military reliability ? mil-std-883 and mil temp ceramic ? mil temp plastic - guaranteed -55c to 125c figure 1: military quickram block diagram 22 ram blocks 1,584 high speed logic cells interf a ce military quickram family data sheet up to 90,000 usable pld ga tes quickram combining performance, densi ty and embedded ram
www.quicklogic.com ? 2007 quicklogic corporation ? ? ? ? ? ? military quickram family data sheet rev. c 2 table 1: military quickram product family member s features ql4016 ql4036 ql4090 max gate s 61, 8 20 97,12 8 176,60 8 logic array 20x16 2 8 x24 44x36 logic cell s 320 672 1,5 8 4 max flip-flop s 43 8 8 76 1,900 max i/o 8 2 174 316 ram module s 10 14 22 ram bit s 11,520 16,12 8 25,344 packages qualification level a,b a. m = military temperature (-55c to +125c) b. / 88 3 = mil s td 88 3 supply voltage ql4016 ql4036 ql4090 cpga m, / 88 3 3.3 v 8 4 - - plcc m 3.3 v 8 4 - - tqfp m, / 88 3 3.3 v - 144 - cqfp m, / 88 3 3.3 v - - 20 8 pqfp m 3.3 v - 20 8 20 8 /240 pbga m 3.3 v - - 456 cqfp m, / 88 3 3.3 v 100 - - table 2: max i/o per device/package combination device 84 cpga 84 plcc 100 cqfp 144 tqfp 208 cqfp 208 pqfp 240 pqfp 456 pbga ql4016 60 60 74 - - - - - ql4036 - - - 110 - 166 - - ql4090 - - - - 166 166 194 30 8
? 2007 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? military quickram family data sheet rev. c 3 architecture overview the military quickram tm family of embedded standard products ( esps) offer fpga logic in combination with dual-port sram modules. the military quickram fa mily of esps have up to 90,000 usable pld gates. military quickram esps are fabricated on a 0.35 m fo ur-layer metal process usin g quicklogic's patented vialink tm technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use. the military quickram family contains a range of 320 to 1,584 logic cells and 10 to 22 dual port ram modules (see figure 1 ). each ram module has 1,152 ram bits, for a total ranging from 11,520 to 25,344 bits (see table 1 ). ram modules are dual port (one read port, one write port) and can be configured into one of four modes: 64 (deep) x18 (w ide), 128x9, 256x4, or 512x2 (see figure 2 ). with a maximum of 316 i/os, the military quickram family of esps are avai lable in many device/package combinations (see table 2 ). figure 2: quickram module designers can cascade multiple ram modules to increas e the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules (see figure 3 ). this approach allows up to 512-deep config urations as large as 16 bits wide in the smallest military quickram device and 44 bits wide in the largest device. figure 3: quickram module bit s wa wd we wclk re rclk ra rd [8:0] [17:0] [8:0] [17:0] mode asyncrd [1:0] rdata wdata raddr rdata waddr wdata ram module (1,152 bit s ) ram module (1,152 bit s )
www.quicklogic.com ? 2007 quicklogic corporation ? ? ? ? ? ? military quickram family data sheet rev. c 4 software support for the complete military quickram family is available through two basic packages. the turnkey quickworks tm package provides the most complete esp so ftware solution from design entry to logic synthesis, to place and route, to simulation. the quicktools tm packages provides a solution for designers who use cadence, exemplar, mentor, synopsys, synplicity, vi ewlogic, aldec, or other third-party tools for design entry, synthesis, or simulation. the quicklogic variable grain logic cell features up to 16 simultaneous inpu ts and 5 outputs within a cell that can be fragmented into 5 in dependent cells. each cell has a fan-in of 29 including register and control lines (see figure 4 ). figure 4: quickram logic cell qs a1 a2 a 3 a4 a5 a6 f1 f2 f 3 f4 f5 f6 qs op b1 b2 c1 c2 mp ms d1 d2 e1 e2 np ns qc qr oz az qz nz fz
? 2007 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? military quickram family data sheet rev. c 5 electrical specifications dc characteristics the dc specifications are provided in table 3 through table 5 . table 3: ab s olute maximum rating s parameter value parameter value v cc voltage -0.5 to 4.6 v dc input current 20 ma v ccio voltage -0.5 to 7.0 v e s d pad protection 2000 v input voltage -0.5 v to v ccio +0.5 v s torage temperature -65 c to +150 c latch-up immunity 200 ma lead temperature 300 c table 4: operating range symbol parameter military unit min. max. v cc s upply voltage 3.0 3.6 v v ccio i/o input tolerance voltage 3.0 5.5 v t a ambient temperature -55 - c t c ca s e temperature - 125 c k delay factor -0 s peed grade 0.42 2.03 n/a -1 s peed grade 0.42 1.64 n/a -2 s peed grade 0.42 1.37 n/a table 5: dc characteri s tic s symbol parameter conditions min. max. units v ih input high voltage 0.5 v cc v ccio + 0.5 v v il input low voltage -0.5 0.3v cc v v oh output high voltage i oh = -12 ma 2.4 v cc v i oh = -500 a 0.9 v cc v cc v v ol output low voltage i ol = 8 ma a a. military device s have 8 ma iol s pecification s . 0.45 v i ol = 1.5 ma 0.1 v cc v i i i or i/o input leakage current v i = v ccio or gnd -10 10 a i oz 3- s tate output leakage current v i = v ccio or gnd -10 10 a c i input capacitance b b. capacitance i s s ample te s ted only. clock pin s are 12 pf maximum. 10 pf i o s output s hort circuit current c v o = gnd -15 -1 8 0 ma v o = v cc 40 210 ma i cc d.c. s upply current d v i , v io = v ccio or gnd 0.50 (typ) 5 ma i ccio d.c. s upply current on v ccio 0 100 a
www.quicklogic.com ? 2007 quicklogic corporation ? ? ? ? ? ? military quickram family data sheet rev. c 6 ac characteristics at v cc = 3.3 v, t a = 25 c (k = 1.00) to calculate delays, multiply the appropriate k factor from table 4 by the numbers provided in table 6 through table 15 . c. only one output at a time. duration s hould not exceed 30 s econd s . d. maximum i cc i s 5 ma all military grade device s . for ac condition s , contact quicklogic cu s tomer engineering. table 6: logic cell symbol parameter propagation delays (ns) fanout 1 2 3 4 5 t pd combinatorial delay a a. the s e limit s are derived from a repre s entative s election of the s lowe s t path s through the quickram logic cell including typical net delay s . wor s t ca s e delay value s for s pecific path s s hould be determined from timing analy s i s of your particular de s ign. 1.4 1.7 1.9 2.2 3.2 t s u s etup time a 1.7 1.7 1.7 1.7 1.7 t h hold time 0.0 0.0 0.0 0.0 0.0 t clk clock to q delay 0.7 1.0 1.2 1.5 2.5 t cwhi clock high time 1.2 1.2 1.2 1.2 1.2 t cwlo clock low time 1.2 1.2 1.2 1.2 1.2 t s et s et delay 1.0 1.3 1.5 1. 8 2. 8 t re s et re s et delay 0. 8 1.1 1.3 1.6 2.6 t s w s et width 1.9 1.9 1.9 1.9 1.9 t rw re s et width 1. 8 1. 8 1. 8 1. 8 1. 8 table 7: ram cell s ynchronou s write timing symbol parameter propagation delays (ns) fanout 1 2 3 4 5 t s wa wa s etup time to wclk 1.0 1.0 1.0 1.0 1.0 t hwa wa hold time to wclk 0.0 0.0 0.0 0.0 0.0 t s wd wd s etup time to wclk 1.0 1.0 1.0 1.0 1.0 t hwd wd hold time to wclk 0.0 0.0 0.0 0.0 0.0 t s we we s etup time to wclk 1.0 1.0 1.0 1.0 1.0 t hwe we hold time to wclk 0.0 0.0 0.0 0.0 0.0 t wcrd wclk to rd (wa=ra) a a. s tated timing for wor s t ca s e propagation delay over proce ss variation at v cc = 3.3 v and t a = 25 c. multiply by the appropriate delay factor, k, for s peed grade, voltage and temperature s etting s a s s pecified in table 4 . 5.0 5.3 5.6 5.9 7.1
? 2007 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? military quickram family data sheet rev. c 7 ta b l e 8 : ram cell s ynchronou s read timing symbol parameter propagation delays (ns) fanout 1 2 3 4 5 t s ra ra s etup time to rclk 1.0 1.0 1.0 1.0 1.0 t hra ra hold time to rclk 0.0 0.0 0.0 0.0 0.0 t s re re s etup time to rclk 1.0 1.0 1.0 1.0 1.0 t hre re hold time to rclk 0.0 0.0 0.0 0.0 0.0 t rcrd rclk to rd a a. s tated timing for wor s t ca s e propagation delay over proce ss variation at v cc = 3.3 v and t a = 25 c. multiply by the appropriate delay factor, k, for s peed grade, voltage and temperature s etting s a s s pecified in table 4 . 4.04.34.64.96.1 table 9: ram cell a s ynchronou s read timing symbol parameter propagation delays (ns) fanout 1 2 3 4 5 rpdrd ra to rd a a. s tated timing for wor s t ca s e propagation delay over proce ss variation at v cc = 3.3 v and t a = 25 c. multiply by the appropriate delay factor, k, for s peed grade, voltage and temperature s etting s a s s pecified in the table 4 . 3.0 3.3 3.6 3.9 5.1 table 10: input-only/clock cell s symbol parameter propagation delays (ns) fanout a a. s tated timing for wor s t ca s e propagation delay over proce ss variation at v cc = 3.3 v and t a = 25 c. multiply by the appropriate delay factor, k, for s peed grade, voltage and temperature s etting s a s s pecified in table 4 . 1 2 3 4 8 12 24 t in high drive input delay 1.5 1.6 1. 8 1.9 2.4 2.9 4.4 t ini high drive input, inverting delay 1.6 1.7 1.9 2.0 2.5 3.0 4.5 t i s u input regi s ter s et-up time 3.1 3.1 3.1 3.1 3.1 3.1 3.1 t ih input regi s ter hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 t iclk input regi s ter clock to q 0.7 0. 8 1.01.11.62.13.6 t ir s t input regi s ter re s et delay 0.6 0.7 0.9 1.0 1.5 2.0 3.5 t ie s u input regi s ter clock enable s etup time 2.3 2.3 2.3 2.3 2.3 2.3 2.3 t ieh input regi s ter clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0
www.quicklogic.com ? 2007 quicklogic corporation ? ? ? ? ? ? military quickram family data sheet rev. c 8 table 11: 4016 clock cell s symbol parameter propagation delays (ns) fanout a a. the array di s tributed network s con s i s t of 40 half column s and the global di s tributed network s con s i s t of 44 half column s , each driven by an independent buffer. the number of half column s u s ed doe s not affect clock buffer delay. the array clock ha s up to 8 load s per half column. the global clock ha s up to 11 load s per half column. 1 2 3 4 8 10 11 t ack array clock delay 1.2 1.2 1.3 1.3 1.5 1.6 1.7 t gckp global clock pin delay 0.7 0.7 0.7 0.7 0.7 0.7 0.7 t gckb global clock buffer delay 0. 8 0. 8 0.90.91.11.21.3 table 12: 4036 clock cell s symbol parameter propagation delays (ns) fanout a a. the array di s tributed network s con s i s t of 56 half column s and the global di s tributed network s con s i s t of 60 half column s , each driven by an independent buffer. the number of half column s u s ed doe s not affect clock buffer delay. the array clock ha s up to 12 load s per half column. the global clock ha s up to 15 load s per half column. 1 2 3 4 8 10 12 15 t ack array clock delay 1.2 1.2 1.3 1.3 1.5 1.6 1.7 1. 8 t gckp global clock pin delay 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 t gckb global clock buffer delay 0. 8 0. 8 0.90.91.11.21.31.4 table 13: 4090 clock cell s symbol parameter propagation delays (ns) fanout a a. the array di s tributed network s con s i s t of 88 half column s and the global di s tributed network s con s i s t of 92 half column s , each driven by an independent buffer. the number of half column s u s ed doe s not affect clock buffer delay. the array clock ha s up to 1 8 load s per half column. the global clock ha s up to 20 load s per half column. 1 2 3 4 8 10 12 14 16 18 20 t ack array clock delay 1.2 1.2 1.3 1.3 1.5 1.6 1.7 1. 8 1.9 2.0 2.1 t gckp global clock pin delay 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 t gckb global clock buffer delay 0. 8 0. 8 0.9 0.9 1.1 1.2 1.3 1.4 1.5 1.6 1.7
? 2007 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? military quickram family data sheet rev. c 9 figure 5: load s u s ed for t pxz table 14: i/o cell input delay s symbol parameter propagation delays (ns) fanout a a. s tated timing for wor s t ca s e propagation delay over proce ss variation at v cc = 3.3 v and t a = 25 c. multiply by the appropriate delay factor, k, for s peed grade, voltage and temperature s etting s a s s pecified in table 4 . 1 2 3 4 8 10 t i/o input delay (bidirectional pad) 1.3 1.6 1. 8 2.1 3.1 3.6 t i s u input regi s ter s et-up time 3.1 3.1 3.1 3.1 3.1 3.1 t ih input regi s ter hold time 0.0 0.0 0.0 0.0 0.0 0.0 t ioclk input regi s ter clock to q 0.7 1.0 1.2 1.5 2.5 3.0 t ior s t input regi s ter re s et delay 0.6 0.9 1.1 1.4 2.4 2.9 t ie s u input regi s ter clock enable s et-up time 2.3 2.3 2.3 2.3 2.3 2.3 t ieh input regi s ter clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 table 15: i/o cell output delay s symbol parameter propagation delays (ns) output load capacitance (pf) 3 50 75 100 150 t outlh output delay low to high 2.1 2.5 3.1 3.6 4.7 t outhl output delay high to low 2.2 2.6 3.2 3.7 4. 8 t pzh output delay tri- s tate to high 1.2 1.7 2.2 2. 8 3.9 t pzl output delay tri- s tate to low 1.6 2.0 2.6 3.1 4.2 t phz output delay high to tri- s tate a a. the load s pre s ented in figure 5 are u s ed for t pxz : 2.0 - - - - t plz output delay high to tri- s tate a 1.2 - - - - 1 k 1 k t t 5pf 5pf phz plz
www.quicklogic.com ? 2007 quicklogic corporation ? ? ? ? ? ? military quickram family data sheet rev. c 10 kv and kt graphs figure 6: voltage factor v s . s upply voltage figure 7: temperature factor v s . operating temperature 0.9200 0.9400 0.9600 0.9800 1.0000 1.0200 1.0400 1.0600 1.0800 1.1000 3 3.1 3.2 3.3 3.4 3.5 3.6 volt a ge f a ctor vs. s u pply volt a ge s u pply volt a ge (v) kv 0.85 0.90 0.95 1.00 1.05 1.10 1.15 -60 -40 -20 0 20 40 60 80 temper a t u re f a ctor vs. oper a ting temper a t u re j u nction temper a t u re c kt
? 2007 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? military quickram family data sheet rev. c 11 power-up sequencing figure 8 : power-up requirement s when powering up a device, the v cc /v ccio rails must take 400 s or long er to reach the maximum value (refer to table 8 ). note: ramping v cc /v ccio to the maximum voltage fa s ter than 400 s can cau s e the device to behave improperly. for users with a limited power budget, keep (v ccio -v cc ) max 500 mv when ramping up the power supply. volt a ge v ccio v cc (v ccio -v cc ) max time 400 u s v cc
www.quicklogic.com ? 2007 quicklogic corporation ? ? ? ? ? ? military quickram family data sheet rev. c 12 jtag figure 9: jtag block diagram microprocessors and application specific integrated ci rcuits (asics) pose many design challenges, not the least of which concerns the accessibilit y of test points. the joint test acce ss group (jtag) formed in response to this challenge, resulting in ieee standard 1149.1, the standard test access port and boundary scan architecture. the jtag boundary scan test methodology allows complete observation and control of the boundary pins of a jtag-compatible device through jtag software. a test access port (tap) controller works in concert with the instruction register (ir); these allow users to run thre e required tests, along with several user-defined tests. jtag tests allow users to reduce syst em debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verification of higher level system elements. the 1149.1 standard requires the following three tests: ? extest instruction. the extest instruction performs a printed circuit board (pcb) interconnect test. this test places a device into an external boundary test mode, selecting the boundary scan register to be connected between the tap test data in (tdi) and te st data out (tdo) pins. boundary scan cells are preloaded with test patterns (via the sample/preload in struction), and input boundary cells capture the input data for analysis. ? sample/preload instruction. the sample/preload instruction allows a device to remain in its functional mode, while selecting the boundary scan register to be connected between the tdi and tdo pins. for this test, the boundary scan register can be accessed via a data scan operation, allowing users to sample the functional data entering and leaving the device. tck tms trstb rdi tdo instr u ction decode a nd control logic tap controller st a te m a chine (16 st a tes) instr u ction register bo u nd a ry-sc a nregister (d a t a register) m u x byp a ss register m u x intern a l register i/o registers user defined d a t a register
? 2007 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? military quickram family data sheet rev. c 13 ? bypass instruction. the bypass instruction allows data to skip a device boundary scan entirely, so the data passes through the bypa ss register. the bypass instruction allows users to test a device without passing through other devices. the bypass register is connected between the tdi and tdo pins, allowing serial data to be transferred through a device withou t affecting the operation of the device. pin descriptions table 16: pin de s cription s pin function description tdi/r s i te s t data in for jtag /ram init. s erial data in hold high during normal operation. connect s to s erial prom data in for ram initialization. connect to v cc if unu s ed. tr s tb/rro active low re s et for jtag /ram init. re s et out hold low during normal operation. connect s to s erial prom re s et for ram initialization. connect to gnd if unu s ed. tm s te s t mode s elect for jtag hold high during normal operation. connect to v cc if not u s ed for jtag. tck te s t clock for jtag hold high or low during normal operation. connect to v cc or ground if not u s ed for jtag. tdo/rco te s t data out for jtag /ram init. clock out connect to s erial prom clock for ram initialization. mu s t be left unconnected if not u s ed for jtag or ram initialization. s tm s pecial te s t mode mu s t be grounded during normal operation. i/aclk high-drive input and/or array network driver can be configured a s either or both. i/gclk high-drive input and/or global network driver can be configured a s either or both. i high-drive input u s e for input s ignal s with high fanout. i/o input/output pin can be configured a s an input and/or output. v cc power s upply pin connect to 3.3 v s upply. v ccio input voltage tolerance pin connect to 5.0 v s upply if 5 v input tolerance i s required, otherwi s e connect to 3.3 v s upply. gnd ground pin connect to ground. gnd/therm ground/thermal pin available on 456-pbga only. connect to ground plane on pcb if heat s inking de s ired. otherwi s e may be left unconnected.
www.quicklogic.com ? 2007 quicklogic corporation ? ? ? ? ? ? military quickram family data sheet rev. c 14 ql4016 ? 84 cpga pinout diagram figure 10: ql4016 ? 8 4 pin cpga (top view) ql4016 ? 84 cpga pinout table table 17: ql4016 ? 8 4 cpga pinout table 84 cpga function 84 cpga function 84 cpga function 84 cpga function a1 i/o b11 i/o f9 i/o k2 i/o a2 i/o c1 vcc f10 i/o k3 i/o a3 i/o c2 i/o f11 i/o k4 i/o a4 i/o c5 vcc g1 i/o k5 gclk/i a5 i/o c6 aclk/i g2 i/o k6 gclk/i a6 i/o c7 gnd g3 vccio k7 gclk/i a7 i/o c10 i/o g9 gnd k8 i/o a8 i/o c11 i/o g10 i/o k9 i/o a9 i/o d1 i/o g11 i/o k10 tck a10 i/o d2 i/o h1 i/o k11 i/o a11 tdo d10 i/o h2 i/o l1 tm s b1 i/o d11 i/o h10 vcc l2 i/o b2 i/tdi e1 i/o h11 i/o l3 i/o b3 i/o e2 i/o j1 i/o l4 i/o b4 i/o e3 gnd j2 tr s tb l5 i/o b5 gclk/i e9 vccio j5 gnd l6 i/o b6 gclk/i e10 i/o j6 aclk/i l7 i/o b7 gclk/i e11 i/o j7 vcc l8 i/o b8 i/o f1 i/o j10 s tm l9 i/o b9 i/o f2 i/o j11 i/o l10 i/o b10 i/o f3 i/o k1 i/0 l11 i/o quickram ql4016-1cg84m
? 2007 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? military quickram family data sheet rev. c 15 ql4016 ? 84 plcc pinout diagram figure 11: ql4016 ? 8 4 pin plcc (top view) ql4016 ? 84 plcc pinout table ta b l e 1 8 : ql4016 ? 8 4 plcc pinout table 84 plcc function 84 plcc function 84 plcc function 84 plcc function 1 i/o 22 aclk/i 43 i/o 64 aclk/i 2 i/o 23 i 44 i/o 65 i 3 i/o 24 gclk/i 45 i/o 66 gclk/i 4 vccio 25 vcc 46 vccio 67 vcc 5 i/o 26 i/o 47 i/o 68 i/o 6 i/o 27 i/o 48 i/o 69 i/o 7 i/o 28 i/o 49 i/o 70 i/o 8 i/o 29 i/o 50 i/o 71 i/o 9 i/o 30 i/o 51 i/o 72 i/o 10 i/o 31 i/o 52 tr s tb 73 i/o 11 tdo 32 i/o 53 tm s 74 i/o 12 i/o 33 tdi 54 i/o 75 tck 13 i/o 34 i/o 55 i/o 76 s tm 14 i/o 35 i/o 56 i/o 77 i/o 15 i/o 36 vcc 57 i/o 78 i/o 16 i/o 37 i/o 58 i/o 79 vcc 17 i/o 38 i/o 59 i/o 80 i/o 18 i/o 39 i/o 60 i/o 81 i/o 19 gnd 40 gnd 61 gnd 82 gnd 20 i/o 41 i/o 62 i/o 83 i/o 21 i 42 i/o 63 i 84 i/o tdo io io io io io io vccio io io io io io gnd io io vcc io io stm tck io io io io io io io vcc gclk/i i aclk/i i io gnd io io io io io io io tdi io io vcc io io io gnd io io io io io vccio io io io io io trstb tms 74 7 3 72 71 70 6 9 68 67 66 65 64 6 3 62 61 60 5 9 58 57 56 55 54 33 3 4 3 5 3 6 3 7 3 8 39 40 41 42 4 3 44 45 46 47 48 4 9 50 51 52 5 3 12 1 3 14 15 16 17 18 1 9 20 21 22 2 3 24 25 26 27 28 2 9 3 0 3 1 3 2 ql4016-1pl84c quickram io io io io io io io gnd io i aclk/i i gclk/i vcc io io io io io io io 11 10 9 87 65 4 3 2 1 84 8 3 82 81 80 7 9 78 77 76 75
www.quicklogic.com ? 2007 quicklogic corporation ? ? ? ? ? ? military quickram family data sheet rev. c 16 ql4016 ? 100 cqfp pinout diagram figure 12: ql4016 ? 100 pin cqfp (top view) quickram QL4016-1CF100M pin 1 pin 76 pin 26 pin 51
? 2007 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? military quickram family data sheet rev. c 17 ql4016 ? 100 cqfp pinout table table 19: ql4016 ? 100 cqfp pinout table 100 cqfp function 100 cqfp function 100 cqfp function 100 cqfp function 1 i/o 26 tdi 51 i/o 76 tck 2 i/o 27 i/o 52 i/o 77 s tm 3 i/o 28 i/o 53 i/o 78 i/o 4 i/o 29 i/o 54 i/o 79 i/o 5 i/o 30 i/o 55 i/o 80 i/o 6 i/o 31 i/o 56 i/o 81 i/o 7 i/o 32 i/o 57 i/o 82 i/o 8 i/o 33 i/o 58 i/o 83 i/o 9 gnd 34 i/o 59 gnd 84 i/o 10 i/o 35 gnd 60 i/o 85 gnd 11 i 36 i/o 61 i 86 i/o 12 aclk/i 37 i/o 62 aclk/i 87 i/o 13 vcc 38 gnd 63 vcc 88 gnd 14 i 39 i/o 64 i 89 i/o 15 gclk/i 40 i/o 65 gclk/i 90 i/o 16 vcc 41 i/o 66 vcc 91 i/o 17 i/o 42 vccio 67 i/o 92 vccio 18 i/o 43 i/o 68 i/o 93 i/o 19 i/o 44 i/o 69 i/o 94 i/o 20 i/o 45 i/o 70 i/o 95 i/o 21 i/o 46 i/o 71 i/o 96 i/o 22 i/o 47 i/o 72 i/o 97 i/o 23 i/o 48 i/o 73 i/o 98 i/o 24 i/o 49 tr s tb 74 i/o 99 i/o 25 i/o 50 tm s 75 i/o 100 tdo
www.quicklogic.com ? 2007 quicklogic corporation ? ? ? ? ? ? military quickram family data sheet rev. c 18 ql4036 ? 144 tqfp pinout diagram figure 13: ql4036 ? 144 pin tqfp (top view) ql4036 ? 208 pqfp pinout diagram figure 14: ql4036 ? 20 8 pin pqfp (top view) pin 1 pin 3 7 pin 7 3 pin 10 9 ql4036-1pf144c quickram pin 1 pin 5 3 pin 105 pin 157 ql4036-1pq208c quickram
? 2007 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? military quickram family data sheet rev. c 19 ql4036 ? 144 tqfp and 208 pqfp pinout table table 20: ql4036 ? 144 tqfp and 20 8 pqfp pinout table 208 pqfp 144 tqfp function 208 pqfp 144 tqfp function 208 pqfp 144 tqfp function 208 pqfp 144 tqfp function 208 pqfp 144 tqfp function 1 nc i/o 43 30 gnd 85 60 i/o 127 87 gnd 169 117 i/o 2 1 i/o 44 31 i/o 86 61 i/o 128 88 i/o 170 118 i/o 3 2 i/o 45 nc i/o 87 nc i/o 129 89 gclk/i 171 119 i/o 4 3 i/o 46 32 i/o 88 62 i/o 130 90 aclk/i 172 120 i/o 5 nc i/o 47 nc i/o 89 63 i/o 131 91 vcc 173 nc i/o 6 4 i/o 48 33 i/o 90 nc i/o 132 92 gclk/i 174 nc i/o 7 5 i/o 49 nc i/o 91 nc i/o 133 93 gclk/i 175 121 i/o 8 nc i/o 50 34 i/o 92 64 i/o 134 94 vcc 176 nc i/o 9 6 i/o 51 35 i/o 93 nc i/o 135 95 i/o 177 122 gnd 10 7 vcc 52 36 i/o 94 65 i/o 136 nc i/o 178 123 i/o 11 nc i/o 53 37 i/o 95 66 gnd 137 96 i/o 179 124 i/o 12 nc gnd 54 38 tdi 96 67 i/o 138 nc i/o 180 nc i/o 13 8 i/o 55 39 i/o 97 nc vcc 139 97 i/o 181 125 i/o 14 nc i/o 56 nc i/o 98 nc i/o 140 98 i/o 182 126 gnd 15 9 i/o 57 40 i/o 99 68 i/o 141 nc i/o 183 127 i/o 16 nc i/o 58 nc i/o 100 69 i/o 142 99 i/o 184 128 i/o 17 10 i/o 59 nc gnd 101 nc i/o 143 nc i/o 185 129 i/o 18 11 i/o 60 41 i/o 102 70 i/o 144 100 i/o 186 nc i/o 19 12 i/o 61 42 vcc 103 71 tr s tb 145 nc vcc 187 130 vccio 20 13 i/o 62 43 i/o 104 72 tm s 146 101 i/o 188 131 i/o 21 nc i/o 63 nc i/o 105 nc i/o 147 102 gnd 189 132 i/o 22 14 i/o 64 44 i/o 106 73 i/o 148 103 i/o 190 nc i/o 23 15 gnd 65 45 i/o 107 nc i/o 149 104 i/o 191 133 i/o 24 16 i/o 66 nc i/o 108 74 i/o 150 nc i/o 192 134 i/o 25 17 gclk/i 67 46 i/o 109 75 i/o 151 105 i/o 193 nc i/o 26 18 aclk/i 68 47 i/o 110 76 i/o 152 106 i/o 194 135 i/o 27 19 vcc 69 48 i/o 111 77 i/o 153 nc i/o 195 136 i/o 28 20 gclk/i 70 nc i/o 112 nc i/o 154 107 i/o 196 nc i/o 29 21 gclk/i 71 49 i/o 113 78 i/o 155 nc i/o 197 137 i/o 30 22 vcc 72 nc i/o 114 79 vcc 156 108 i/o 198 nc i/o 31 23 i/o 73 50 gnd 115 80 i/o 157 109 tck 199 138 gnd 32 nc i/o 74 51 i/o 116 nc gnd 158 110 s tm 200 139 i/o 33 24 i/o 75 52 i/o 117 81 i/o 159 111 i/o 201 nc vcc 34 nc i/o 76 nc i/o 118 82 i/o 160 nc i/o 202 140 i/o 35 25 i/o 77 53 i/o 119 nc i/o 161 112 i/o 203 nc i/o 36 nc i/o 78 54 gnd 120 83 i/o 162 113 i/o 204 141 i/o 37 26 i/o 79 55 i/o 121 nc i/o 163 nc gnd 205 142 i/o 38 27 i/o 80 56 i/o 122 84 i/o 164 nc i/o 206 nc i/o 39 28 i/o 81 nc i/o 123 85 i/o 165 114 vcc 207 143 tdo 40 nc i/o 82 57 i/o 124 nc i/o 166 115 i/o 208 144 i/o 41 nc vcc 83 58 vccio 125 86 i/o 167 116 i/o 42 29 i/o 84 59 i/o 126 nc i/o 168 nc i/o
www.quicklogic.com ? 2007 quicklogic corporation ? ? ? ? ? ? military quickram family data sheet rev. c 20 ql4090 ? 208 pqfp/cqfp pinout diagram figure 15: ql4090 ? 20 8 pin pqfp/cqfp (top view) ql4090 ? 240 pqfp pinout diagram figure 16: ql4090 ? 240 pin pqfp (top view) pin 1 pin 5 3 pin 105 pin 157 ql4090-1pq208c quickram pin 1 pin 61 pin 121 pin 181 ql4090-1pq240c quickram
? 2007 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? military quickram family data sheet rev. c 21 ql4090 ? 208 pqfp/cqfp and 240 pqfp pinout table table 21: ql4090 ? 20 8 pqfp/cqfp and 240 pqfp pinout table 240 pqfp 208 pqfp/ cqfp function 240 pqfp 208 pqfp/ cqfp function 240 pqfp 208 pqfp/ cqfp function 240 pqfp 208 pqfp/ cqfp function 240 pqfp 208 pqfp/ cqfp function 1 208 i/o 51 43 gnd 98 84 i/o 145 125 i/o 194 168 i/o 2 1 i/o 52 44 i/o 99 85 i/o 146 126 i/o 195 169 i/o 3 2 i/o 53 45 i/o 100 86 i/o 147 127 gnd 196 nc i/o 4 3 i/o 54 46 i/o 101 87 i/o 148 128 i/o 197 170 i/o 5 4 i/o 55 47 i/o 102 88 i/o 149 nc i/o 198 171 i/o 6 5 i/o 56 48 i/o 103 89 i/o 150 129 glck/i 199 172 i/o 7 nc i/o 57 nc i/o 104 90 i/o 151 130 aclk/i 200 173 i/o 8 6 i/o 58 49 i/o 105 91 i/o 152 131 vcc 201 174 i/o 9 7 i/o 59 50 i/o 106 92 i/o 153 132 glck/i 202 175 i/o 10 8 i/o 60 51 i/o 107 nc i/o 154 133 glck/i 203 nc i/o 11 9 i/o nc 52 i/o 108 93 i/o 155 134 vcc 204 176 i/o 12 10 vcc nc 53 i/o 109 94 i/o 156 135 i/o 205 177 gnd 13 11 i/o 61 54 tdi 110 95 gnd 157 136 i/o 206 178 i/o 14 12 gnd 62 nc i/o nc 96 i/o 158 nc i/o 207 179 i/o 15 13 i/o 63 nc i/o 111 97 vcc 159 137 i/o 208 nc i/o 16 14 i/o 64 55 i/o nc 98 i/o 160 nc gnd 209 180 i/o 17 nc i/o 65 56 i/o nc 99 i/o 161 138 i/o 210 181 i/o 18 15 i/o 66 nc i/o 112 100 i/o 162 139 i/o 211 182 gnd 19 16 i/o 67 57 i/o 113 nc i/o 163 140 i/o 212 nc vcc 20 17 i/o 68 58 i/o 114 101 i/o 164 141 i/o 213 183 i/o 21 18 i/o 69 59 gnd 115 nc i/o 165 142 i/o 214 184 i/o 22 19 i/o 70 60 i/o 116 102 i/o 166 nc i/o 215 185 i/o 23 20 i/o 71 61 vcc 117 nc i/o 167 143 i/o 216 186 i/o 24 nc i/o 72 62 i/o 118 nc i/o 168 144 i/o 217 187 vccio 25 21 i/o 73 63 i/o 119 103 tr s tb 169 145 vcc 218 188 i/o 26 22 i/o 74 64 i/o 120 104 tm s 170 nc i/o 219 nc i/o 27 23 gnd 75 nc i/o 121 105 i/o 171 146 i/o 220 189 i/o 28 24 i/o 76 65 i/o 122 nc i/o 172 147 gnd 221 190 i/o 29 25 gclk/i 77 66 i/o 123 106 i/o 173 148 i/o 222 191 i/o 30 26 aclk/i 78 67 i/o 124 107 i/o 174 149 i/o 223 192 i/o 31 27 vcc 79 nc i/o 125 108 i/o 175 150 i/o 224 193 i/o 32 28 gclk/i 80 68 i/o 126 109 i/o 176 151 i/o 225 194 i/o 33 29 gclk/i 81 69 i/o 127 nc i/o 177 152 i/o 226 nc i/o 34 30 vcc 82 70 i/o 128 110 i/o 178 153 i/o 227 195 i/o 35 31 i/o 83 nc i/o 129 111 i/o 179 154 i/o 228 196 i/o 36 32 i/o nc 71 i/o 130 112 i/o 180 155 i/o 229 197 i/o 37 nc gnd 84 nc i/o 131 113 i/o nc 156 i/o 230 198 i/o 38 33 i/o 85 72 i/o 132 114 vcc 181 157 tck 231 nc i/o 39 nc i/o 86 73 gnd 133 115 i/o 182 158 s tm 232 199 gnd 40 34 i/o 87 74 i/o 134 116 gnd 183 nc i/o 233 200 i/o 41 35 i/o 88 nc vcc 135 117 i/o 184 159 i/o 234 201 vcc 42 36 i/o 89 75 i/o 136 nc i/o 185 160 i/o 235 202 i/o 43 nc i/o 90 76 i/o 137 118 i/o 186 161 i/o 236 203 i/o 44 37 i/o 91 77 i/o 138 119 i/o 187 162 i/o 237 204 i/o 45 38 i/o 92 78 gnd 139 120 i/o 188 163 gnd 238 205 i/o 46 39 i/o 93 79 i/o 140 121 i/o 189 164 i/o 239 206 i/o 47 nc i/o 94 80 i/o 141 nc i/o 190 165 vcc 240 207 tdo 48 40 i/o 95 81 i/o 142 122 i/o 191 166 i/o 49 41 vcc 96 82 i/o 143 123 i/o 192 nc i/o 50 42 i/o 97 83 vccio 144 124 i/o 193 167 i/o
www.quicklogic.com ? 2007 quicklogic corporation ? ? ? ? ? ? military quickram family data sheet rev. c 22 ql4090 ? 456 pbga pinout diagram figure 17: ql4090 ? 456 pbga pinout diagram ql4090-1pb456c quickram bottom view top view pin a1 corner 26 25 24 2 3 22 21 20 19 1 8 17 16 15 14 1 3 12 11 10 9 8 76 5 4 3 21 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af
? 2007 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? military quickram family data sheet rev. c 23 ql4090 ? 456 pbga pinout table table 22: ql4090 ? 456 pbga pinout table 456 pbga function 456 pbga function 456 pbga function 456 pbga function 456 pbga function a1 i/o c1 i/o e1 i/o h23 i/o m23 nc a2 i/o c2 i/o e2 i/o h24 i/o m24 i/o a3 i/o c3 i/o e3 i/o h25 i/o m25 i/o a4 i/o c4 tdo e4 i/o h26 i/o m26 i/o a5 i/o c5 i/o e5 gnd j1 i/o n1 gclk/i a6 i/o c6 i/o e6 vcc j2 i/o n2 i/o a7 i/o c7 i/o e7 gnd j3 i/o n3 i/o a8 i/o c8 i/o e8 nc j4 nc n4 gclk/i a9 i/o c9 i/o e9 gnd j5 gnd n5 vcc a10 i/o c10 i/o e10 i/o j22 nc n11 gnd/therm a11 i/o c11 i/o e11 gnd j23 nc n12 gnd/therm a12 vccio c12 i/o e12 gnd j24 i/o n13 gnd/therm a13 i/o c13 i/o e13 vcc j25 i/o n14 gnd/therm a14 i/o c14 i/o e14 gnd j26 i/o n15 gnd/therm a15 i/o c15 i/o e15 gnd k1 i/o n16 gnd/therm a16 i/o c16 i/o e16 gnd k2 i/o n22 gnd a17 i/o c17 i/o e17 nc k3 i/o n23 i/o a18 i/o c18 i/o e18 gnd k4 i/o n24 i/o a19 i/o c19 i/o e19 nc k5 vcc n25 i/o a20 i/o c20 i/o e20 gnd k22 gnd n26 i/o a21 i/o c21 i/o e21 vcc k23 i/o p1 i/o a22 i/o c22 i/o e22 gnd k24 i/o p2 i/o a23 i/o c23 i/o e23 i/o k25 i/o p3 i/o a24 i/o c24 i/o e24 i/o k26 i/o p4 i/o a25 i/o c25 tck e25 i/o l1 i/o p5 nc a26 i/o c26 i/o e26 i/o l2 i/o p11 gnd/therm b1 i/o d1 i/o f1 i/o l3 i/o p12 gnd/therm b2 i/o d2 i/o f2 i/o l4 i/o p13 gnd/therm b3 i/o d3 i/o f3 i/o l5 nc p14 gnd/therm b4 i/o d4 gnd f4 nc l11 gnd/therm p15 gnd/therm b5 i/o d5 i/o f5 vcc l12 gnd/therm p16 gnd/therm b6 i/o d6 nc f22 vcc l13 gnd/therm p22 nc b7 i/o d7 i/o f23 nc l14 gnd/therm p23 gclk/i b8 i/o d8 i/o f24 i/o l15 gnd/therm p24 gclk/i b9 i/o d9 gnd f25 i/o l16 gnd/therm p25 i/o b10 i/o d10 i/o f26 i/o l22 nc p26 aclk/i b11 i/o d11 i/o g1 i/o l23 i/o r1 i/o b12 i/o d12 gnd g2 i/o l24 i/o r2 i/o b13 i/o d13 i/o g3 i/o l25 i/o r3 i/o b14 i/o d14 i/o g4 i/o l26 i/o r4 nc b15 i/o d15 gnd g5 nc m1 aclk/i r5 nc b16 i/o d16 i/o g22 gnd m2 gclk/i r11 gnd/therm b17 i/o d17 i/o g23 i/o m3 i/o r12 gnd/therm b18 i/o d18 gnd g24 i/o m4 nc r13 gnd/therm b19 i/o d19 i/o g25 i/o m5 gnd r14 gnd/therm b20 i/o d20 i/o g26 i/o m11 gnd/therm r15 gnd/therm b21 i/o d21 nc h1 i/o m12 gnd/therm r16 gnd/therm b22 i/o d22 i/o h2 i/o m13 gnd/therm r22 vcc b23 i/o d23 gnd h3 i/o m14 gnd/therm r23 nc b24 i/o d24 i/o h4 i/o m15 gnd/therm r24 i/o b25 i/o d25 i/o h5 nc m16 gnd/therm r25 i/o b26 s tm d26 i/o h22 nc m22 nc r26 gclk/i
www.quicklogic.com ? 2007 quicklogic corporation ? ? ? ? ? ? military quickram family data sheet rev. c 24 t1 i/o w5 nc ab15 vcc ad3 i/o ae17 i/o t2 i/o w22 nc ab16 i/o ad4 i/o ae18 i/o t3 i/o w23 i/o ab17 nc ad5 i/o ae19 i/o t4 i/o w24 i/o ab18 vcc ad6 i/o ae20 i/o t5 vcc w25 i/o ab19 gnd ad7 i/o ae21 i/o t11 gnd/thermal w26 i/o ab20 nc ad8 i/o ae22 i/o t12 gnd/thermal y1 i/o ab21 vcc ad9 i/o ae23 nc t13 gnd/thermal y2 i/o ab22 gnd ad10 i/o ae24 tm s t14 gnd/thermal y3 i/o ab23 i/o ad11 i/o ae25 i/o t15 gnd/thermal y4 i/o ab24 i/o ad12 i/o ae26 i/o t16 gnd/thermal y5 i/o ab25 i/o ad13 i/o af1 i/o t22 gnd y22 gnd ab26 i/o ad14 i/o af2 i/o t23 i/o y23 i/o ac1 i/o ad15 i/o af3 i/o t24 i/o y24 i/o ac2 i/o ad16 i/o af4 i/o t25 i/o y25 i/o ac3 nc ad17 i/o af5 i/o t26 i/o y26 i/o ac4 gnd ad18 i/o af6 i/o u1 i/o aa1 i/o ac5 i/o ad19 i/o af7 i/o u2 i/o aa2 i/o ac6 nc ad20 i/o af8 i/o u3 i/o aa3 nc ac7 i/o ad21 i/o af9 i/o u4 i/o aa4 nc ac8 i/o ad22 i/o af10 i/o u5 gnd aa5 vcc ac9 nc ad23 tr s tb af11 i/o u22 nc aa22 vcc ac10 i/o ad24 i/o af12 i/o u23 i/o aa23 nc ac11 i/o ad25 i/o af13 i/o u24 i/o aa24 i/o ac12 nc ad26 i/o af14 i/o u25 i/o aa25 i/o ac13 i/o ae1 tdi af15 i/o u26 i/o aa26 i/o ac14 vccio ae2 i/o af16 i/o v1 i/o ab1 i/o ac15 nc ae3 i/o af17 i/o v2 i/o ab2 i/o ac16 i/o ae4 i/o af18 i/o v3 i/o ab3 i/o ac17 i/o ae5 i/o af19 i/o v4 nc ab4 i/o ac18 nc ae6 i/o af20 i/o v5 nc ab5 gnd ac19 i/o ae7 i/o af21 i/o v22 gnd ab6 vcc ac20 i/o ae8 i/o af22 i/o v23 nc ab7 nc ac21 i/o ae9 i/o af23 i/o v24 i/o ab8 nc ac22 nc ae10 i/o af24 i/o v25 i/o ab9 nc ac23 gnd ae11 i/o af25 i/o v26 i/o ab10 vcc ac24 i/o ae12 i/o af26 i/o w1 i/o ab11 gnd ac25 i/o ae13 i/o w2 i/o ab12 nc ac26 i/o ae14 i/o w3 i/o ab13 i/o ad1 i/o ae15 i/o w4 i/o ab14 gnd ad2 nc ae16 i/o table 22: ql4090 ? 456 pbga pinout table (continued) 456 pbga function 456 pbga function 456 pbga function 456 pbga function 456 pbga function
? 2007 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? military quickram family data sheet rev. c 25 package mechanical drawings 84 cpga mechanical drawing
www.quicklogic.com ? 2007 quicklogic corporation ? ? ? ? ? ? military quickram family data sheet rev. c 26 84 plcc mechanical drawing
? 2007 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? military quickram family data sheet rev. c 27 100 cqfp mechanical drawing
www.quicklogic.com ? 2007 quicklogic corporation ? ? ? ? ? ? military quickram family data sheet rev. c 28 144 tqfp packaging drawing
? 2007 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? military quickram family data sheet rev. c 29 208 pqfp mechanical drawing
www.quicklogic.com ? 2007 quicklogic corporation ? ? ? ? ? ? military quickram family data sheet rev. c 30 208 cqfp mechanical drawing
? 2007 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? military quickram family data sheet rev. c 31 240 pqfp mechanical drawing
www.quicklogic.com ? 2007 quicklogic corporation ? ? ? ? ? ? military quickram family data sheet rev. c 32 240 pqfp mechanical drawing (continued)
? 2007 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? military quickram family data sheet rev. c 33 456 pbga mechanical drawing
www.quicklogic.com ? 2007 quicklogic corporation ? ? ? ? ? ? military quickram family data sheet rev. c 34 packaging information the quickram product family packag ing information is presented in table 23 . note: military temperature range pla s tic package s will be added a s follow on product s to the commercial and indu s trial product s . ordering information table 23: packaging option s device information device ql4016 ql4036 ql4090 pin pitch pin pitch pin pin package definition s a a. plcc = pla s tic leaded chip carrier pqfp = pla s tic quad flat pack pbga = pla s tic ball grid array tqfp = thin quad flat pack cqfp = ceramic quad flat pack cpga = ceramic pin grid array 8 4 cpga 0.10 mm 144 tqfp 0.5 mm 20 8 cqfp 0.5 mm 8 4 plcc 0.05 in. 20 8 pqfp 0.5 mm 20 8 pqfp 0.5 mm 100 cqfp 0.025 in. 240 pqfp 0.5 mm - - - - 456 pbga 1.27 mm ql 40 9 0 -1 pq208 m oper a ting r a nge: m = milit a ry p a ck a ge code: cg84 = 84-pin cpga pf84 = 84-pin plcc cf100 = 100-pin cqfp pf144 = 144-pin tqfp pq208 = 208-pin pqfp cf208 = 208-pin cqfp pq240 = 240-pin pqfp pb456 = 456- ba ll pbga p a rt n u m b er: q u icklogic device speed gr a de: 0-q u ick 1-f a st 2-f a ster 4016, 40 3 6, 40 9 0
? 2007 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? military quickram family data sheet rev. c 35 contact information phone: (408) 990-4000 (us) (905) 940-4149 (canada) +(44) 1932 57 9011 (europe) +(86) 21 6867 0273 (asia ? except japan) +(81) 45 470 5525 (japan) e-mail: info@quicklogic.com sales: www.quicklogic.com/sales support: www.quicklogic.com/support internet: www.quicklogic.com revision history copyright and trademark information copyright ? 2007 quicklogic corpor ation. all rights reserved. the information contained in this document is protected by copyright. all righ ts are reserved by quicklogic corporation. quickl ogic corporation reserves the right to modify this document without an y obligation to notify any person or entity of such revision. copying, duplicating, selling, or otherwis e distributing any part of this product without the prior written consent of an authorized rep resentative of quicklogic is prohibited. quicklogic and the quicklogic logo , vialink, quickram, and quickworks are registered trademarks of quicklogic corporation; quicktools and spde are trademar ks of quicklogic corporation. verilog is a registered trademark of cadence design systems, inc. revision date originator and comments a not available not available b july 2006 mehul kochar and kathleen murchek updated format and content. c s eptember 2007 mehul kochar and kathleen murchek updated mechanical drawing s .

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